1. Field of the Invention
The present invention relates to a DRAM control circuit, particularly to a DRAM control circuit which supports high speed page mode.
2. Description of the Related Art
Among semiconductor memory devices, a DRAM (Dynamic Random Access Memory) is commonly used in microcomputer system in recent years. Configuration commonly used in the DRAM is such that an address is inputted after being divided into a row address and a column address for time sharing operation in order to reduce the number of pins, wherein a #RAS signal is used as a strobe signal for the row address and a #CAS signal is used as a strobe signal for the column address.
Symbol "#" in the names of the #RAS signal and the #CAS signal indicates that the signal is low-active.
The DRAM requires that each memory cell thereof is refreshed within a specified time interval. Among a plurality of methods of refreshing which are known for the present DRAM, #CAS-before-#RAS method is a relatively simple method.
A DRAM control circuit of the prior art wherein the #CAS-before-#RAS method is employed will be described below.
FIG. 1 is a block diagram showing an example of configuration of the DRAM control circuit of the prior art as described above which is built in a microprocessor.
In FIG. 1, numeral 50 denotes a microprocessor building in a conventional DRAM control circuit, 52 denotes a DRAM connected to the microprocessor 50, 51 denotes a CPU provided in the microprocessor 50. To the CPU 51, a data bus 1, an address bus 4, a clock signal line 9, a trigger signal line 22 and a read/write signal line 23 are connected.
The data bus 1 is connected to an external data bus 24 via a reading tri-state buffer and a writing tri-state buffer indicated by numerals 2 and 3, respectively, for the data inputting/outputting between the CPU 51 and the DRAM 52. The external data bus 24 is connected to an external terminal 61 of the microprocessor 50, while the external terminal 61 is further connected to an external terminal 71 of the DRAM 52. The reading tri-state buffer 2 and the writing tri-state buffer 3 are controlled by a signal generating circuit 15 to be described later.
The address bus 4 is provided for the purpose of sending from the CPU 51 to the DRAM 52 the address of data in the DRAM 52 to be inputted/outputted to/from the DRAM 52 via the data bus 1. The address bus 4 is connected to an external address bus 19 via a multiplexer 5. The external address bus 19 is connected to an external terminal 62 of the microprocessor 50, and the external terminal 62 is further connected to an external terminal 72 of the DRAM 52.
The multiplexer 5 time-divides an address, which is outputted from the CPU 51 onto the address bus 4, into a row address and a column address and outputs them to the external address bus 19. The multiplexer 5 is controlled by the signal generating circuit 15 to be described later.
To the clock signal line 9, a counter 10 is connected via a frequency divider 90. The frequency divider 90 divides a clock .phi. outputted from the CPU 51, and outputs pulse signals.
The counter 10 is a down counter in this example, and decrements its count value every time it receives a pulse from the frequency divider 90. Initial value of the counter 10 is given from by a reload register 11. Specifically, the value held by the reload register 11 is given to the counter 10 as the initial value every time the counter 10 underflows.
The frequency divider 90, the counter 10 and the reload register 11 constitute a timer circuit 100 which serves as timing means for generating a refresh request signal REFREQ of the DRAM 52 at specified constant time intervals. The refresh request signal REFREQ is generated at the timing when the counter 10 underflows and is initialized by the value held in the reload register 11, and is given to the signal generating circuit 15 via the refresh request signal line 101.
The signal generating circuit 15 generates the #RAS signal and the #CAS signal and, as described previously, controls the tri-state buffers 2, 3 and the multiplexer 5. Numeral 17 in the signal generating circuit 15 denotes a timing circuit which determines the timing of generating the #RAS signal and the #CAS signal, and numeral 18 denotes a trigger holding circuit which holds a trigger signal representing an access request given from the CPU 51 via a trigger signal line 22.
The #RAS signal generated by the signal generating circuit 15 is outputted to the external terminal 63 via an output signal line 20, and the #CAS signal is outputted to the external terminal 64 via an output signal line 21. The external terminals 63 and 64 of the microprocessor 50 are connected to the external terminals 73 and 74 of the DRAM 52 respectively.
Numeral 23 denotes a read/write signal line over which read/write signal R/#W, in the state of "0" when reading data from the DRAM 52 or in the state of "1" when writing data into the DRAM 52, is outputted from the CPU 51. The read/write signal line 23 is connected to an external terminal 65 as well as to the signal generating circuit 15 while the external terminal 65 is connected to an external terminal 75 of the DRAM 52.
The circuit shown in FIG. 1 requires the CPU 51 to set an appropriate value in the reload register 11 before starting the operation. Specifically, the CPU 51 sets such a value in the reload register 11 via the signal line 110 that the counter 10 underflows and the refresh request signal REFREQ is generated at a time interval of ten and several microseconds to satisfy a refreshing condition of the DRAM 52.
Internal configuration of the DRAM 52 is known to those skilled in the art, and the description thereof will be omitted.
Operation of the DRAM control circuit of the prior art wherein the #CAS-before-#RAS method as shown in FIG. 1 is employed is carried out as described below. It is assumed that an appropriate value is set in the reload register 11 by the CPU 51, as described above.
When a trigger signal representing the access request is inputted to the signal generation circuit 15 from the CPU 51 via the trigger signal line 22, the signal generation circuit 15 determines whether to read data from the DRAM 52 or to write data onto the DRAM 52, according to the state of the read/write signal line 23, that is, "1" or "0".
At first, the operation when the read/write signal R/#W is "1", namely when data is read from the DRAM 52, will be described below.
Because a row address is outputted onto the external address bus 19 usually, the signal generating circuit 15 at first activates the #RAS signal which is outputted therefrom onto the signal line 20. By this fact, the DRAM 52 recognizes the row address outputted onto the external address bus 19. Then the signal generating circuit 15 controls the multiplexer 5 thereby to switch the signal on the external address bus 19 to a column address, and thereafter the signal generating circuit 15 activates the #CAS signal which is outputted onto the signal line 21. By this fact, the DRAM 52 recognizes the column address outputted onto the external address bus 19.
Because the DRAM 52 starts the operation of reading data as described above, data outputted from the DRAM 52 is sent from the external data bus 24 to the CPU 51 via the reading tri-state buffer 2 and the data bus 1, when the signal generating circuit 15 turns the reading tri-state buffer to conducting state.
Thereafter, when the signal generating circuit 15 activates the #CAS signal outputted therefrom onto the signal line 21 and then activates the #RAS signal outputted therefrom onto the signal line 20, the operation of reading data from the DRAM 52 is completed.
Now the operation when the read/write signal R/#W is "0", namely when data is written onto the DRAM 52, will be described below.
At first, the signal generating circuit 15 activates the #RAS signal outputted therefrom onto the signal line 20, thereby to make the DRAM 52 recognize the row address. Then the signal generating circuit 15 controls the multiplexer 5 thereby to switch the signal on the external address bus 19 to a column address. The signal generating circuit 15 then turns the writing tri-state buffer 3 to conducting state thereby to send the data having been outputted onto the data bus 1 by the CPU 51 to the DRAM 52 and, at the same time, activates the #CAS signal to make the DRAM 52 recognize the column address. By this fact, the DRAM 52 starts writing operation of the data, which is outputted onto the external data bus 24 from the CPU 51 via the data bus 1 and the writing tri-state buffer 3, into itself. Thereafter, the signal generating circuit 15 activates the #CAS signal outputted therefrom onto the signal line 21 and negates the #RAS signal outputted therefrom onto the signal line 20, thereby to complete the operation of writing data onto the DRAM 52.
Now operation at refreshing will be described below.
Refreshing of the DRAM 52 by the #CAS-before-#RAS method is carried out by activating the #CAS signal earlier than the #RAS signal. Therefore, when the refresh request signal REFREQ is outputted from the timer circuit 100 onto the refresh request signal line 101, the signal generating circuit 15 at first activates the #CAS signal, then activates the #RAS signal, followed by negating of the #CAS signal and, at last, negating of the #RAS signal. The DRAM 52 is refreshed during the interval from the time when both the #CAS signal and the #RAS signal are activated to the time when the #CAS signal is negated.
When a conflict arises between the refresh request signal REFREQ outputted from the timer circuit 100 and the trigger signal outputted from the CPU 51, the signal generating circuit 15 executes refreshing of the DRAM 52 giving priority thereto.
There has been such a problem with a DRAM that it has low access rates although they have large storage capacities. In order to solve this problem, several high-speed access methods have been developed. In the high-speed page mode among one of these methods, when the same address is accessed repetitively, the #RAS signal is kept at "0", and the second and the following accesses are made by means of the #CAS signal while sending only the column address to the DRAM 52.
FIG. 2 is a block diagram showing a configuration example of the conventional DRAM control circuit built in a microprocessor employing such a page mode as described above.
Portions of the configuration shown in FIG. 2 which are different from the configuration shown in FIG. 1 will be described below.
To the address bus 4, a page address register 6 is connected via an electrical switch 7. The page address register 6 holds the row address portion (higher part) of the address outputted onto the address bus 4 from the CPU 51 when the electrical switch 7 opens (conducts) at a predetermined timing.
The row address portion of the address held by the page address register 6 is given to a comparator 8. To the comparator 8, an address is also directly inputted from the address bus 4, and the comparator 8 compares both addresses to check whether they coincide or not. In other words, the comparator 8 compares the row address portion at the present address and the row address portion of the address given when the electrical switch 7 opens. Result of comparison by the comparator 8 is given to the signal generating circuit 15. The result of comparison by the comparator 8 is reset to the state of coincidence by a predetermined procedure described later, after being held temporarily.
The signal generating circuit 15 is provided with a flip-flop (F/F) represented by numeral 16 therein. The flip-flop 16 holds an information indicating whether paging or not. Specifically, the flip-flop 16 is set to "1" when the comparator 8 determines that both addresses coincide. In other words, when the higher portion (row address) of the address held by the page address register 6 and the higher part (row address) of the address which is outputted from the CPU 51 at this time coincide with each other, it is in the state of high-speed paging wherein access can be started by activating the #CAS signal (this state will be hereinafter called the state of paging).
In the DRAM control circuit of such a configuration as shown in FIG. 2, when the higher portion (row address) of the address outputted from the CPU 51 at a certain timing and the higher portion (row address) of the address which is outputted from the CPU 51 at every timing later coincide, the state of coincidence is detected by the comparator 8 and stored in the flip-flop 16 (the flip-flop 16 is set to "1"). Under this state wherein the flip-flop is set, because the same address of the DRAM 52 is accessed successively, the signal generating circuit 15 keeps the #RAS signal at "0" and sends only the column address to the DRAM 52 in the second and the following accesses, thereby making continuous accesses by outputting only the #CAS signal. Such a state of access to the DRAM 52 is the high-speed page mode.
In the case where the DRAM is accessed in the high-speed page mode as described above, and refresh request is generated, the high-speed page mode is once canceled resulting in a problem of reduced efficiency of access.
Also when a DRAM of different storage capacity is used, or different bit constitution is employed (for example, .times.1 bit or .times.4 bits) resulting in different bit width of the address, a microprocessor comprising a DRAM cannot be designed with the DRAM control circuit of the same configuration. Thus it is required to design a DRAM control circuit exclusively for different configuration of the DRAM, resulting in increased manufacturing cost.